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| DS1251Y DS1251Y 4096K NV SRAM with Phantom Clock FEATURES PIN ASSIGNMENT A18/RST A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 * Real time clock keeps track of hundredths of seconds, minutes, hours, days, date of the month, months, and years * 512K x 8 NV SRAM directly replaces volatile static RAM or EEPROM * Embedded lithium energy cell maintains calendar operation and retains RAM data * Watch function is transparent to RAM operation * Month and year determine the number of days in each month; valid up to 2100 * Standard 32-pin JEDEC pinout * Full 10% operating range * Operating temperature range 0C to 70C * Accuracy is better than 1 minute/month @ 25C * Over 10 years of data retention in the absence of power 32-PIN ENCAPSULATED PACKAGE 740 MIL FLUSH PIN DESCRIPTION A0-A18 CE GND DQ0-DQ7 VCC WE OE RST - - - - - - - - Address Inputs Chip Enable Ground Data In/Data Out Power (+5V) Write Enable Output Enable Reset * Available in 120 ns and 150 ns access time ORDERING INFORMATION DS1251Y-120 DS1251Y-150 120 ns access 150 ns access DESCRIPTION The DS1251Y 4096K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 512K words by 8 bits) with a built-in real time clock. The DS1251Y has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of- tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent garbled data in both the memory and real time clock. The Phantom Clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with less than 31 days, including correction for leap years. The Phantom Clock operates in either 24-hour or 12-hour format with an AM/PM indicator. ECopyright 1997 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. 032697 1/12 DS1251Y RAM READ MODE The DS1251Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) is active (low). The unique address specified by the 17 address inputs (A0-A18) defines which of the 512K bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE for OE rather than address access. PHANTOM CLOCK OPERATION Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. All accesses which occur prior to recognition of the 64-bit pattern are directed to memory. After recognition is established, the next 64 read or write cycles either extract or update data in the Phantom Clock, and memory access is inhibited. Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of Chip Enable (CE), Output Enable (OE), and Write Enable (WE). Initially, a read cycle to any memory location using the CE and OE control of the Phantom Clock starts the pattern recognition sequence by moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the Phantom Clock. Therefore, any address to the memory in the socket is acceptable. However, the write cycles generated to gain access to the Phantom Clock are also writing data to a location in the mated RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched (this bit pattern is shown in Figure 1). With a correct match for 64-bits, the Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom Clock. RAM WRITE MODE The DS1251Y is in the write mode whenever the WE and CE signals are in the active (low) state after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1251Y provides full functional capability for VCC greater than 4.5 volts and write protects by approximately 4.0 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAM constantly monitors VCC. Should the supply voltage decay, the RAM automatically write protects itself. All inputs to the RAM become "don't care" and all outputs are high impedance. As VCC falls below approximately 3.0 volts, the power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.5 volts. 032697 2/12 DS1251Y PHANTOM CLOCK REGISTER INFORMATION The Phantom Clock information is contained in eight registers of 8-bits, each of which is sequentially accessed one bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the Phantom Clock registers, each register must be handled in groups of 8-bits. Writing and reading individual bits within a register could produce erroneous results. These read/write registers are defined in Figure 2. Data contained in the Phantom Clock register is in binary coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. PHANTOM CLOCK REGISTER DEFINITION Figure 1 7 BYTE 0 1 6 1 5 0 4 0 3 0 2 1 1 0 0 1 HEX VALUE C5 BYTE 1 0 0 1 1 1 0 1 0 3A BYTE 2 1 0 1 0 0 0 1 1 A3 BYTE 3 0 1 0 1 1 1 0 0 5C BYTE 4 1 1 0 0 0 1 0 1 C5 BYTE 5 0 0 1 1 1 0 1 0 3A BYTE 6 1 0 1 0 0 0 1 1 A3 BYTE 7 0 1 0 1 1 1 0 0 5C NOTE: The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated and causing inadvertent entry to the Phantom Clock is less than 1 in 1019. This pattern is sent to the Phantom Clock LSB to MSB. 032697 3/12 DS1251Y PHANTOM CLOCK REGISTER DEFINITION Figure 2 REGISTER 7 0 6 0.1 SEC 5 4 3 2 1 0.01 SEC 0 00-99 RANGE (BCD) 1 0 10 SEC SECONDS 00-59 2 0 10 MIN MINUTES 00-59 3 12/24 0 10 A/P HR HOUR 01-12 00-23 4 0 0 OSC RST 0 DAY 01-07 5 0 0 10 DATE DATE 01-31 6 0 0 0 10 MONTH MONTH 01-12 7 10 YEAR YEAR 00-99 AM-PM/12/24 MODE Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). to logic 0, a low input on the RESET pin will cause the Phantom Clock to abort data transfer without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These bits are shipped from the factory set to a logic 1. OSCILLATOR AND RESET BITS Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET bit is set ZERO BITS Registers 1, 2, 3, 4, 5, and 6 contain one or more bits which will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable. 032697 4/12 DS1251Y ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C -40C to +70C 260C for 10 seconds (See Note 13) * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Power Supply Voltage Input Logic 1 Input Logic 0 SYMBOL VCC VIH VIL MIN 4.5 2.2 -0.3 TYP 5.0 MAX 5.5 VCC+0.3 +0.8 UNITS V V V (0C to 70C) NOTES DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current I/O Leakage Current CE VIH VCC Output Current @ 2.4 volts Output Current @ 0.4 volts Standby Current CE = 2.2 volts Standby Current CE = VCC - 0.5 volts Operating Current tCYC = 200 ns SYMBOL IIL IIO IOH IOL ICCS1 ICCS2 ICC01 MIN -1.0 -1.0 -1.0 2.0 5.0 3.0 TYP (0C to 70C; VCC = 5V 10%) MAX +1.0 +1.0 UNITS A A mA mA 10 5.0 85 mA mA mA NOTES 12 DC TEST CONDITIONS Outputs are open; all voltages are referenced to ground. CAPACITANCE PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN TYP 5 5 MAX 10 10 UNITS pF pF (tA = 25C) NOTES 032697 5/12 DS1251Y MEMORY AC ELECTRICAL CHARACTERISTICS DS1251Y-120 (0C to 70C; VCC = 5.0V 10%) DS1251Y-150 PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time from WE SYMBOL MIN tRC tACC tOE tCO tCOE tOD toH tWC tWP tAW tWR tODW tOEW tDS tDH 5 50 20 5 120 90 0 20 40 5 60 20 5 40 5 150 100 0 20 70 120 120 60 120 5 70 MAX MIN 150 150 70 150 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 5 5 3 5 5 4 4 AC TEST CONDITIONS Output Load: Input Pulse Levels: 50 pF + 1TTL Gate 0-3 volts Timing Measurement Reference Levels Input: 1.5 volts Output: 1.5 volts Input Pulse Rise and Fall Times: 5 ns 032697 6/12 DS1251Y PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS PARAMETER Read Cycle Time CE Access Time OE Access Time CE to Output Low Z OE to Output Low Z CE to Output High Z OE to Output High Z Read Recovery Write Cycle Time Write Pulse Width Write Recovery Data Setup Time Data Hold Time CE Pulse Width RESET Pulse Width CE High to Power-Fail SYMBOL tRC tCO tOE tCOE tOEE tOD tODO tRR tWC tWP tWR tDS tDH tCW tRST tPF 20 120 100 20 40 10 100 200 10 10 MIN 120 TYP (0C to 70C; VCC = 4.5 to 5.5V) MAX UNITS ns 100 100 ns ns ns ns 40 40 ns ns ns ns ns ns ns ns ns ns 0 ns 10 11 11 5 5 NOTES POWER-DOWN/POWER-UP TIMING PARAMETER CE at VIH before Power-Down VCC Slew from 4.5V to 0 volts (CE at VIH) VCC Slew from 0V to 4.5 volts (CE at VIH) CE at VIH after Power-Up SYMBOL tPD tF tR tREC MIN 0 300 0 2 TYP MAX UNITS s s s ms NOTES (tA = 25C) PARAMETER Expected Data Retention Time SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 9 WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. 032697 7/12 DS1251Y MEMORY READ CYCLE (NOTE 1) tRC ADDRESSES VIH VIL tACC VIH tCO VIH VIH VIL VIH VIL tOH CE OE DOUT MEMORY WRITE CYCLE 1 (NOTES 2, 6, AND 7) ADDRESS CE WE DQ0-DQ7 VIH VIL 032697 8/12 III III III III IIIIIIIII IIIIIII IIIIIIIII IIIIIII IIIIIIII IIIIII IIIIIIII IIIIII VIL tOD VIH tOE VIH VIL tCOE tOD tCOE VOH VOL OUTPUT DATA VALID VOH VOL tWC VIH VIL tAW VIH VIL VIH VIL VIL tWP VIL VIH tODW HIGH IMPEDANCE tDS DATA IN STABLE tDH VIH VIL IIIIIIII IIIIIIII tWR VIH tOEW IIII IIII IIIIIIIII IIIIIIIII DS1251Y MEMORY WRITE CYCLE 2 (NOTES 2 AND 8) WE = VIH tWC VIH VIL tAW tWP tWR VIH VIL tOEW VIH VIL VIH VIL ADDRESSES WE VIL tODW VIL tCOE DQ0-DQ7 VIH VIL tDS DATA IN STABLE RESET FOR PHANTOM CLOCK tRST RST READ CYCLE TO PHANTOM CLOCK tRC tCO CE tRR tOE OE tOEE tCOE Q OUTPUT DATA VALID IIIIIIII IIIIIIII tDH VIH VIL tOD tODO III III IIIIIIIII I IIIIIIIII III IIII CE VIH VIL III III 032697 9/12 DS1251Y WRITE CYCLE TO PHANTOM CLOCK OE = VIH tWC tWR tWP WE tWR tCW CE tDS tDH DATA IN STABLE tDH D POWER-DOWN/POWER-UP CONDITION VCC 4.50V 3.2V tF tPD tR tREC CE LEAKAGE CURRENT IL SUPPLIED FROM LITHIUM CELL DATA RETENTION TIME tDR 032697 10/12 IIIIII IIIIII IIIIIII IIIIIII DS1251Y NOTES: 1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH, tDS are measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 50 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output buffers remain in a high impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 9. The expected tDR is defined as accumulative time in the absence of VCC with the clock oscillator running. 10. tWR is a function of the latter occurring edge of WE or CE. 11. tDH and tDS are a function of the first occurring edge of WE or CE. 12. RST (Pin1) has an internal pull-up resistor. 13. Real-Time Clock Modules can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85C. Post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. 032697 11/12 DS1251Y DS1251Y 4096K NV SRAM WITH PHANTOM CLOCK PKG DIM A IN. MM B IN. MM A C IN. MM D IN. MM E IN. MM C F IN. MM F D K G G IN. MM H IN. MM J IN. MM K IN. MM 32-PIN MIN 1.720 43.69 0.720 18.29 0.395 10.03 0.090 2.29 0.017 0.43 0.120 3.05 0.090 2.29 0.590 14.99 0.008 0.20 0.015 0.38 MAX 1.740 44.20 0.740 18.80 0.415 10.54 0.120 3.05 0.030 0.76 0.160 4.06 0.110 2.79 0.630 16.00 0.012 0.30 0.021 0.53 1 J E H B 032697 12/12 |
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